EP910LC-32 vs EP910ILC-25 Comparison
Detailed side-by-side comparison of EP910LC-32 by Altera and EP910ILC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-32 | EP910ILC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | 900 gates (typical) | — |
| Number of Dedicated Inputs | 10 | — |
| Number of I/O Pins | 20 | — |
| Package | PLCC-32 | 44-pin JLCC (windowed ceramic) |
| Speed Grade | -32 | — |
| Maximum Toggle Frequency (fMAX) | [DATA_NEEDED: fMAX value in MHz for -32 grade] | — |
| Pin-to-Pin Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns for -32 grade] | — |
| Supply Voltage (VCC) | 5 V | — |
| Logic Family | Low-power CMOS (LC suffix) | — |
| Programming Method | UV-erasable or one-time programmable (OTP for LC windowless variant) | — |
| Operating Temperature Range | [DATA_NEEDED: commercial or industrial grade] | — |
| I/O Standard | TTL-compatible | — |
| Mounting Type | Surface Mount (PLCC socket or direct solder) | Surface Mount |
| RoHS Status | unknown | non_compliant (ceramic windowed package) |
| MSL Level | unknown | — |
| Family | — | EP910 Classic EPLD |
| Macrocells | — | 24 |
| User I/O Pins | — | 36 |
| Propagation Delay (tPD) | — | 25 ns |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Operating Temperature | — | -40C to +85C (industrial) |
| Supply Voltage | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Lifecycle Status | — | Obsolete - last time buy was late 1990s |