EP910LC-35 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910LC-35 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-35 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic (EP910) | Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 30 ns (max) |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EPROM | — |
| Package | PLCC-44 (J-lead, LC suffix) | DIP-40 (through-hole, 600 mil) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Pin Count | 44 | — |
| Programmable Flip-Flops | Yes (per macrocell) | — |
| Output Enable Control | Per macrocell | — |
| Erasure Method | UV (windowed) or OTP (plastic) | — |
| RoHS Status | Not applicable (legacy product) | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Dedicated Inputs | — | 36 |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Supply Voltage | — | 5 V |
| Process Technology | — | CMOS |
| Programming Method | — | UV-Erasable / OTP |
| Mounting Type | — | Through-Hole |