EP910LC-35 vs EP910LC-35T Comparison
Detailed side-by-side comparison of EP910LC-35 by Altera and EP910LC-35T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-35 | EP910LC-35T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic (EP910) | Classic EPLD (EP910) |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| Technology | CMOS EPROM | — |
| Package | PLCC-44 (J-lead, LC suffix) | PLCC-44 (J-lead) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Pin Count | 44 | — |
| Programmable Flip-Flops | Yes (per macrocell) | — |
| Output Enable Control | Per macrocell | — |
| Erasure Method | UV (windowed) or OTP (plastic) | UV-erasable window (ceramic package) / OTP (plastic) |
| RoHS Status | Not applicable (legacy product) | [DATA_NEEDED: RoHS status not in verified data] |
| Logic Capacity | — | 450 usable gates |
| Maximum Operating Frequency | — | 28.6 MHz |
| User I/O Pins | — | 36 |
| Process Technology | — | CMOS (EPROM-based) |
| Programming | — | Altera programming hardware + MAX+PLUS II |
| Mounting Type | — | Surface Mount (PLCC socket or solder) |
| MSL Level | — | MSL 3 (168 hours) |