EP910LC-35T vs EP910LC-35 Comparison
Detailed side-by-side comparison of EP910LC-35T by Altera and EP910LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-35T | EP910LC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Classic EPLD (EP910) | Classic (EP910) |
| Logic Capacity | 450 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Operating Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| User I/O Pins | 36 | — |
| Package | PLCC-44 (J-lead) | PLCC-44 (J-lead, LC suffix) |
| Process Technology | CMOS (EPROM-based) | — |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) | UV (windowed) or OTP (plastic) |
| Programming | Altera programming hardware + MAX+PLUS II | — |
| Mounting Type | Surface Mount (PLCC socket or solder) | — |
| MSL Level | MSL 3 (168 hours) | — |
| RoHS Status | [DATA_NEEDED: RoHS status not in verified data] | Not applicable (legacy product) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Technology | — | CMOS EPROM |
| Pin Count | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |