EP910LC44-35 vs EP910LC44-30T Comparison
Detailed side-by-side comparison of EP910LC44-35 by Intel and EP910LC44-30T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC44-35 | EP910LC44-30T |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Classic EPLD (OT sub-family) | — |
| Architecture | PAL-type AND/OR array | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns (max) | 33 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Total Inputs | 36 | 36 |
| I/O Pins | 24 | — |
| Global Clocks | 2 | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (nominal 5 V) |
| Operating Temperature | 0C to +70C (commercial) | — |
| Package | 44-pin PLCC (J-leaded) | PQCC-44 (Plastic Leaded Chip Carrier, J-bend) |
| Mounting Type | Surface Mount | Surface Mount |
| Process Technology | CMOS | — |
| Programmability | UV-erasable (windowed ceramic) | — |
| Device Family | — | Classic EPLD |
| Logic Type | — | PAL-type CMOS EPLD (OT PLD) |
| Product Terms | — | 240 |
| Dedicated Inputs | — | 12 |
| I/O Lines | — | 24 (bidirectional) |
| Total Outputs | — | 24 |
| External Clock Inputs | — | 2 |
| Programming Technology | — | CMOS, UV-erasable (windowed package in family) |
| Security Bit | — | Programmable (logic readback protection) |
| Operating Temperature Grade | — | Commercial |
| Terminal Form | — | J-BEND |
| Package Code | — | QCCJ |