EP910LC44-35 vs EP910LI-35BF Comparison
Detailed side-by-side comparison of EP910LC44-35 by Intel and EP910LI-35BF by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC44-35 | EP910LI-35BF |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Classic EPLD (OT sub-family) | — |
| Architecture | PAL-type AND/OR array | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns (max) | — |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Total Inputs | 36 | — |
| I/O Pins | 24 | — |
| Global Clocks | 2 | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V (nominal) |
| Operating Temperature | 0C to +70C (commercial) | — |
| Package | 44-pin PLCC (J-leaded) | 44-pin PLCC (J-lead) |
| Mounting Type | Surface Mount | — |
| Process Technology | CMOS | — |
| Programmability | UV-erasable (windowed ceramic) | — |
| Device Family | — | Altera Classic EPLD |
| Part Number Base | — | EP910 |
| Logic Density | — | 450 usable gates |
| Maximum Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency (fmax) | — | 28.6 MHz |
| Operating Temperature Range | — | Industrial (LI suffix) |
| Technology | — | CMOS, UV-erasable |
| Programming Method | — | EPROM/UV-erase programmer (Altera Classic algorithm) |
| Output Polarity Control | — | Programmable XOR per macrocell |
| Flip-Flop Type | — | Selectable D/T/JK/SR per macrocell |
| TTL Compatibility | — | 100% TTL emulation |
| Compliance / EOL Status | — | Obsolete - last-time buy exhausted; second-source via Rochester Electronics |