EP910LI-12 vs EP910IPC-12 Comparison
Detailed side-by-side comparison of EP910LI-12 by Altera and EP910IPC-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-12 | EP910IPC-12 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 450 |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Frequency (fMAX) | 76.9 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V typical) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Pins | 24 | 24 |
| Inputs (with input registers) | 36 | — |
| Package | 28-PLCC (windowed ceramic, J-Lead) | 40-pin PDIP |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Process Technology | 1.0-micron CMOS EPROM | — |
| Power Dissipation (typical) | 200 mW at 5 V | — |
| Programming Method | UV-erasable via windowed package | — |
| Logic Compatibility | TTL-compatible I/O | — |
| RoHS Status | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS status] |
| Family | — | Classic EPLD |
| Maximum Operating Frequency (fMAX) | — | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 12 ns |
| Dedicated Inputs | — | 10 |
| Mounting Type | — | Through Hole |
| Technology | — | CMOS EPLD (UV-erasable or OTP) |
| Programming Toolchain | — | MAX+PLUS II |
| Logic Capacity | — | Equivalent to ~24 PAL16V8s |