EP910PC-20 vs EP910PC-0 Comparison
Detailed side-by-side comparison of EP910PC-20 by Altera and EP910PC-0 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-20 | EP910PC-0 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Device | EP910 | — |
| Usable Gates | 900 | 900 gates |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Package | PDIP-24 (PC suffix) | PDIP-40 (Plastic DIP, 40-pin) |
| Pin Count | 24 | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| I/O Compatibility | 100% TTL | — |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | EPROM programmer, JEDEC fuse map | UV-erasable / OTP |
| Mounting Type | Through-Hole (DIP) | Through-Hole (DIP) |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Logic Blocks | — | 6 (4 macrocells each) |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 24 |
| Speed Grade | — | -0 (slowest) |
| Supply Voltage | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |