EP910PC30T vs EP910PC-20 Comparison
Detailed side-by-side comparison of EP910PC30T by Altera and EP910PC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC30T | EP910PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Series | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of I/O Pins | 24 | — |
| Number of Dedicated Inputs | 12 | — |
| Maximum Product Terms | 240 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| Process Technology | CMOS | — |
| Programmable Logic Architecture | PAL-type sum-of-products, EPLD | — |
| Package | 24-pin PDIP (PC) | PDIP-24 (PC suffix) |
| Mounting Type | Through-Hole (THT) | Through-Hole (DIP) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Speed Grade | -30 (30 ns tPD) | — |
| Programming Technology | EPROM (OTP in plastic package, UV-erasable in windowed package) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Pin Count | 24 | 24 |
| Device | — | EP910 |
| Usable Gates | — | 900 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| Programming Method | — | EPROM programmer, JEDEC fuse map |
| MSL Level | — | [DATA_NEEDED: MSL level] |