EP910PI-35T vs EP910PC-25 Comparison
Detailed side-by-side comparison of EP910PI-35T by Altera and EP910PC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-35T | EP910PC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 900 |
| Pin-to-Pin Logic Delay (tpd) | 35 ns | — |
| Counter Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V +/- 10% |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Process Technology | CMOS | — |
| Package | 40-pin PDIP (Plastic DIP) | PDIP-24 (Plastic DIP) |
| Mounting Type | Through-Hole | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Programming Method | UV-erasable, EPROM technology | — |
| On-board Test Circuitry | Yes (logic test mode for AC verification) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Product Family | — | Classic EPLD |
| Integration Gates (typical) | — | 4800 |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Maximum Operating Frequency (fMAX) | — | 33.3 MHz |
| Technology | — | CMOS EPROM |
| Pin Count | — | 24 |
| Dedicated Inputs | — | 10 |
| Dedicated I/O Pins | — | 12 |
| TTL Compatibility | — | 100% TTL emulation |
| Erasure Method | — | Not erasable in plastic package (windowless) |