EPC160C100 vs EPC144LC20 Comparison
Detailed side-by-side comparison of EPC160C100 by Altera and EPC144LC20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC160C100
EPC160C100 - Altera Enhanced Configuration Device | Intel FPGA
EPC160C100 ObsoleteIntel
EPC144LC20
EPC144LC20 - 144KB Serial Config PROM, 20-LCC | Intel (Altera)
EPC144LC20 β Last Time BuySpecification Comparison
| Parameter | EPC160C100 | EPC144LC20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | Memory ICs | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.20 | $7.10 |
| Device Type | Enhanced Configuration Device (EPC) for SRAM-based LUT FPGAs | β |
| Supported FPGA Families | Altera APEX, Cyclone, Stratix, and other SRAM-based LUT devices | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K |
| Configuration Density | 160 Mbit equivalent tier | β |
| Operating Voltage (Core) | 3.3 V | β |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | β |
| Configuration Interface | Serial / Parallel, Altera nCONFIG/nSTATUS/CONF_DONE protocol | β |
| Package | PQFP-100 | 20-pin LCC (Leadless Chip Carrier, JLCC-20) |
| Pin Count | 100 | 20 |
| Mounting Type | Surface Mount | Surface Mount |
| Cascade Support | Yes (nCASC pin for multi-FPGA daisy chain) | β |
| Memory Technology | Flash-based non-volatile configuration memory | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| MSL Level | [DATA_NEEDED: MSL rating] | 3 (168 hours) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status per Intel PCN] |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes |
| Memory Capacity | β | 144 Kbit |
| Memory Organization | β | Serial (one-time programmable) |
| Interface Type | β | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Programming Method | β | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) |
| Supply Voltage (VCC) | β | 3.0 V to 5.5 V |
| Configuration Time (typical) | β | [DATA_NEEDED: configuration time at DCLK = 10 MHz] |
| Active Supply Current | β | [DATA_NEEDED: ICC active] |
| Standby Supply Current | β | [DATA_NEEDED: ICC standby] |
| Halogen-Free | β | [DATA_NEEDED] |
| JTAG Compliance | β | IEEE Std 1149.1 |