EPC2LC20N-W vs EPC2LC20 Comparison
Detailed side-by-side comparison of EPC2LC20N-W by Altera and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LC20N-W | EPC2LC20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.45 | $7.20 |
| Memory Type | EPROM (UV-erasable, ISP) | Non-volatile configuration PROM |
| Memory Size | 1.6 Mbit | 1.6 Mbit |
| Programmable Type | In System Programmable | β |
| Configuration Interface | Serial (DATA, DCLK, OE, nCS) | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Internal Oscillator Frequency | 66.7 MHz | β |
| Supply Voltage (VCC) | 3.0 V to 3.6 V, 4.75 V to 5.25 V | β |
| ISP Interface | JTAG (IEEE 1149.1) | β |
| Supported FPGA Families | APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, Cyclone | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Package | 20-LCC (J-Lead) PLCC-20 | 20-pin PLCC (J-lead, 9x9 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Packaging | Tape & Reel (-W suffix) | β |
| Cascade Support | Yes (with other EPC2 devices) | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Pin Count | 20 | β |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS status for -W variant] | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Programming Interface | β | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | β | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | β | 5.0 V or 3.3 V |
| RoHS Status | β | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free Version | β | EPC2LC20N available as lead-free equivalent |
| Programming Support | β | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | β | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |