EPF10K200SBI356-2 vs EPF10K200SBC356-2 Comparison

Detailed side-by-side comparison of EPF10K200SBI356-2 by Altera and EPF10K200SBC356-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPF10K200SBI356-2 EPF10K200SBC356-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Family FLEX 10KS FLEX 10KS (Embedded Programmable Logic)
Logic Elements 9,984 —
System Gates 200,000 200,000
Logic Array Blocks (LABs) 1,248 1248
Embedded Array Blocks (EABs) 24 (98,304 bits RAM) —
User I/O Pins 274 —
Process Technology 0.22 µm CMOS SRAM 0.22 um CMOS
Core Voltage 2.5 V —
Speed Grade -2 -2
Package 356-BGA (SB) 35×35 mm, 1.27 mm pitch 356-LBGA (FineLine BGA, 35 x 35 mm, 1.27 mm pitch)
Mounting Type Surface Mount Surface Mount
Maximum User I/O 274 —
Operating Temperature [DATA_NEEDED: operating temperature range] 0C to +70C (Commercial)
In-System Programmability Yes (JTAG/ByteBlaster) —
Configuration Method SRAM-based, ISP —
MSL Level [DATA_NEEDED: MSL rating] —
RoHS Status [DATA_NEEDED: RoHS status] Non-compliant (legacy part)
Series — FLEX 10KS
Logic Elements / Cells — 9984
Embedded Memory Bits (EAB) — 98304
User I/Os — 274
Number of I/O Banks — 8
Supply Voltage (Core) — 2.5 V (2.375 V - 2.625 V)
I/O Voltage (PCI-compatible) — 3.3 V / 5.0 V tolerant
Propagation Delay — 0.4 ns (per datasheet)
Configuration — SRAM-based (volatile, requires configuration device)
Boundary Scan — Yes (JTAG IEEE 1149.1)
PLL — Yes (on-chip)

Datasheets & Resources

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