EPF10K200SFI672-2B vs EPF10K200SFC672-2 Comparison

Detailed side-by-side comparison of EPF10K200SFI672-2B by Altera and EPF10K200SFC672-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPF10K200SFI672-2B EPF10K200SFI672-2B - 200K Gates FLEX 10KE FPGA | Altera

EPF10K200SFI672-2B - 200K Gates FLEX 10KE FPGA | Altera

EPF10K200SFI672-2B Obsolete

Specification Comparison

Parameter EPF10K200SFI672-2B EPF10K200SFC672-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family FLEX 10KE —
Logic Elements 9,984 9,984
System Gates 200,000 200,000
Maximum System Gates 513,000 —
Embedded Memory 98,304 bits —
Embedded Array Blocks (EABs) 24 (96 Kbits total) —
User I/Os 470 —
Process Technology 0.22 µm CMOS, SRAM 0.22 µm CMOS
Core Supply Voltage 2.5 V 2.5 V (2.375 V to 2.625 V)
Maximum Operating Frequency 200 MHz 200 MHz
PLLs 4 —
Package FBGA-672 (FineLine BGA, 27 × 27 mm, 1.0 mm pitch) 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch
Mounting Type Surface Mount —
Operating Temperature -40 °C to +85 °C (Industrial) 0 °C to +70 °C (Commercial)
Programming Memory Type SRAM —
RoHS Status Non-compliant (legacy FLEX 10KE) [DATA_NEEDED: RoHS compliance status]
Series — FLEX 10KE
Logic Array Blocks (LABs) — 1,248
User I/O Pins — 470
Embedded Memory (bits) — 98,304
I/O Supply Voltage — MultiVolt 2.5 V / 3.3 V / 5.0 V
Speed Grade — -2
Internal Propagation Delay — 0.4 ns
Configuration Method — SRAM-based, passive parallel asynchronous
Boundary Scan — IEEE 1149.1 (JTAG)
On-chip PLL — Yes

Datasheets & Resources

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