EPF8636ARC208-3 vs EPF8636ARC208-4 Comparison
Detailed side-by-side comparison of EPF8636ARC208-3 by Altera and EPF8636ARC208-4 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPF8636ARC208-3
EPF8636ARC208-3 - FLEX 8000 FPGA 6K Gates 208-RQFP | Altera
EPF8636ARC208-3 ObsoleteAltera
EPF8636ARC208-4
EPF8636ARC208-4 - FLEX 8000 FPGA, 6K Gates, 208-RQFP | Altera
EPF8636ARC208-4 ObsoleteSpecification Comparison
| Parameter | EPF8636ARC208-3 | EPF8636ARC208-4 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.95 | $16.50 |
| Series | FLEX 8000 | β |
| Family | FLEX 8000 (FLEX 8K) | β |
| Typical Gate Count | 6,000 gates | β |
| Logic Elements / Cells | 504 | β |
| Number of User I/O | 136 | β |
| Operating Frequency (max) | 125 MHz | β |
| Supply Voltage | 4.75 V to 5.25 V (5 V nominal) | β |
| Technology | CMOS SRAM, 0.42 um process | β |
| Speed Grade | -3 | -4 |
| Package | 208-RQFP (28x28 mm) with exposed pad | 208-RQFP (28x28 mm) with exposed pad |
| Package Category | 208-BFQFP Exposed Pad | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to +70 C (commercial) | -40 C to +105 C |
| RoHS Status | Non-compliant per distributor listing | Non-compliant (legacy 5 V family) |
| Configuration Method | SRAM, loaded via serial EPROM or download cable | Serial configuration EEPROM (in-system) |
| Product Family | β | FLEX 8000 |
| Device Series | β | EPF8636A |
| Usable Gates | β | 6,000 |
| Logic Elements | β | 136 |
| Flip-Flops (Registers) | β | 504 |
| Maximum User I/O | β | 218 |
| Embedded RAM Blocks | β | 8 x 256 x 8 bits |
| Logic Block Type | β | 4-input LUT with fast-carry chain |
| Supply Voltage (VCCINT) | β | 4.75 V to 5.25 V |
| I/O Voltage Tolerance | β | 3.3 V or 5 V |
| Process Technology | β | 5 V CMOS, 0.42 um |
| JTAG / Boundary Scan | β | IEEE 1149.1 compliant |