EPM3032A-TC44-10N vs EPM3032ALC44-10N Comparison

Detailed side-by-side comparison of EPM3032A-TC44-10N by Altera and EPM3032ALC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3032A-TC44-10N EPM3032ALC44-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Manufacturer Altera (now Intel) —
Series MAX 3000A —
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 32 32
Usable Gates 600 —
Logic Elements / LABs 2 Logic Array Blocks —
User I/O Pins 34 34
Number of Pins 44 —
Package 44-pin TQFP 44-pin PLCC (J-Lead, surface mount)
Pin-to-Pin Delay (tPD) 10 ns (commercial speed grade) —
Counter Frequency (fCNT) up to 227.3 MHz —
Supply Voltage (VCCINT) 3.3 V 3.3 V
Programming Technology EEPROM (in-system programmable via JTAG / IEEE 1532) —
Output Enables 6 global OE signals —
Operating Temperature [DATA_NEEDED: operating temperature range] [DATA_NEEDED: industrial/commercial range]
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: compliant or non-compliant]
Mounting Type Surface Mount Surface Mount
Process Technology CMOS EEPROM —
Product Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 600 gates
Logic Array Blocks (LABs) — 2
Propagation Delay (tPD) — 10 ns
Internal fMAX — 103.1 MHz
I/O Voltage (VCCIO) — 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O)
Technology — CMOS EEPROM-based
In-System Programmability — Yes, via IEEE 1149.1 JTAG
ISP Standard Compliance — IEEE Std. 1532
Boundary-Scan Test (BST) — Yes, IEEE 1149.1 compliant

Datasheets & Resources

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