EPM3064ATC100-10N vs EPM3064ATC100-7 Comparison

Detailed side-by-side comparison of EPM3064ATC100-10N by Altera and EPM3064ATC100-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC100-10N EPM3064ATC100-7
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 64
Logic Array Blocks (LABs) 2 2
Maximum User I/O Pins 66 —
Usable Gates 1,250 1,250
Pin-to-Pin Delay (tPD) 10 ns —
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) —
In-System Programmability Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 —
Boundary-Scan Test (BST) Yes - JTAG compliant —
Configuration Memory Non-volatile EEPROM —
Program/Erase Cycles 100 minimum —
MultiVolt I/O Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant —
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
Package 100-pin TQFP 100-pin TQFP
Mounting Type Surface Mount Surface Mount
RoHS Status Compliant (lead-free) —
Maximum User I/Os — 66 (in 100-pin TQFP)
Pin-to-Pin Propagation Delay (tPD) — 7.5 ns (-7 speed grade)
Maximum Internal Counter Frequency — 135.1 MHz
Supply Voltage - VCCINT (Core) — 3.3 V
Supply Voltage - VCCIO (I/O) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
Technology — CMOS EEPROM
In-System Programming (ISP) — Yes, via IEEE 1149.1 JTAG
PCI Compliance — PCI Local Bus Specification Revision 2.2
JTAG Boundary Scan — Yes
Lead Free / RoHS — Compliant (modern shipments)

Datasheets & Resources

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