EPM3064ATI44-10 vs EPM3064ATC44-10 Comparison

Detailed side-by-side comparison of EPM3064ATI44-10 by Intel and EPM3064ATC44-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI44-10 EPM3064ATC44-10
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Programmable Type In-System Programmable (ISP), EEPROM-based —
Number of Macrocells 64 —
Number of Logic Array Blocks (LABs) 4 —
Number of Usable Gates 1,250 —
Number of User I/O Pins 34 —
Package TQFP-44 (10x10 mm, 0.8 mm pitch) TQFP-44, 10 x 10 mm, 0.8 mm pitch
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Counter Frequency 227.3 MHz —
Supply Voltage (VCCINT) 3.3 V 3.0 V to 3.6 V (3.3 V typical)
I/O Voltage Tolerance 5.0 V tolerant (MultiVolt I/O) —
JTAG Interface IEEE Std. 1149.1 compliant —
ISP Standard IEEE Std. 1532 —
Operating Temperature -40C to +85C (Industrial) —
RoHS Status Non-Compliant (contains lead, per DigiChip listing) Non-compliant (legacy Altera, Pb-bearing)
Lead Free Status Contains Lead —
Mounting Type Surface Mount Surface Mount
Process Technology CMOS, EEPROM —
Programming Cycles [DATA_NEEDED: typical program/erase endurance] —
Logic Elements / Macrocells — 64 macrocells
Usable Gates — 1,250
Number of Logic Blocks / LABs — 4 LABs
Propagation Delay (tPD) — 10 ns
Maximum Internal Frequency — 227.3 MHz (counter speed)
Programmable I/Os — 34
I/O Bank Voltage (VCCIO) — MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V
Technology — CMOS EEPROM, 5 V tolerant I/O
In-System Programming — IEEE Std. 1532 (JTAG)
Boundary-Scan Support — IEEE 1149.1 (JTAG)
Operating Temperature Range — 0C to +70C (commercial)

Datasheets & Resources

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