EPM3064ATI44-10 vs EPM3064ATC44-4N Comparison

Detailed side-by-side comparison of EPM3064ATI44-10 by Intel and EPM3064ATC44-4N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI44-10 EPM3064ATC44-4N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND NRND
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Programmable Type In-System Programmable (ISP), EEPROM-based —
Number of Macrocells 64 —
Number of Logic Array Blocks (LABs) 4 —
Number of Usable Gates 1,250 —
Number of User I/O Pins 34 —
Package TQFP-44 (10x10 mm, 0.8 mm pitch) 44-pin TQFP
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Counter Frequency 227.3 MHz 222.2 MHz
Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Voltage Tolerance 5.0 V tolerant (MultiVolt I/O) —
JTAG Interface IEEE Std. 1149.1 compliant —
ISP Standard IEEE Std. 1532 —
Operating Temperature -40C to +85C (Industrial) 0C to +70C (commercial)
RoHS Status Non-Compliant (contains lead, per DigiChip listing) [DATA_NEEDED: rohs status]
Lead Free Status Contains Lead —
Mounting Type Surface Mount Surface Mount
Process Technology CMOS, EEPROM —
Programming Cycles [DATA_NEEDED: typical program/erase endurance] —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 64
Logic Array Blocks — 2
Number of I/Os — 34
Dedicated Inputs — 4
Usable Gates — 1,250
Propagation Delay (tpd) — 4.5 ns
I/O Supply Voltage (VCCIO) — 2.5 V or 3.3 V
Programmability — EEPROM, in-system programmable (JTAG)
JTAG Support — IEEE Std. 1149.1 (boundary-scan) and IEEE Std. 1532 (ISP)

Datasheets & Resources

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