EPM3256AFC256-10N vs EPM3128AFC256-7N Comparison
Detailed side-by-side comparison of EPM3256AFC256-10N by Altera and EPM3128AFC256-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3256AFC256-10N | EPM3128AFC256-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Usable Gates | 5,000 gates | 2,500 |
| Macrocells | 256 | — |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Voltage | 3.3 V | — |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | In-system (ISP), IEEE Std. 1532, JTAG (IEEE Std. 1149.1) |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| Package | 256-pin FineLine BGA | 256-BGA (FineLine, FBGA) |
| Logic Family | CMOS | CMOS |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | — |
| Operating Temperature | 0 C to 70 C (commercial) | 0 C to +70 C (commercial) |
| Architecture | — | CMOS EEPROM-based MAX |
| Macro Cells | — | 128 |
| User I/Os | — | 98 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Internal fMAX | — | 192.3 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 3.3 V or 2.5 V |
| Mounting Type | — | Surface Mount |