EPM3256AQC208-10 vs EPM3512AQC210-10 Comparison

Detailed side-by-side comparison of EPM3256AQC208-10 by Altera and EPM3512AQC210-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC210-10

EPM3512AQC210-10 - MAX 3000A CPLD, 512 Macrocells, PQFP-210 | Altera

EPM3512AQC210-10 Nrnd

Specification Comparison

Parameter EPM3256AQC208-10 EPM3512AQC210-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $15.20 $25.40
Family MAX 3000A MAX 3000A
Logic Family CMOS (EEPROM-based) β€”
Macrocells 256 β€”
Usable Gates 5,000 β€”
User I/Os 161 β€”
Number of Pins 208 β€”
Package 208-BFQFP (PQFP, Gull Wing) PQFP-210
Pin-to-Pin Propagation Delay 10 ns β€”
Counter Frequency (max) 227.3 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Tolerance MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant β€”
Programming Interface IEEE 1149.1 JTAG (ISP) JTAG (IEEE 1149.1) / ISP
Operating Temperature 0 Β°C to +70 Β°C (Commercial) 0C to +70C (commercial)
PCI-SIG Compliance Yes (speed grades -4, -5, -6, -7, -10) β€”
Global Clock Networks 4 (CLK, CLR, OE, GCLK) β€”
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs_compliance_status]
Device Type β€” CPLD (Complex Programmable Logic Device)
Logic Macrocells β€” 512
Logic Array Blocks (LABs) β€” 16 (32 macrocells each)
Maximum User I/O Pins β€” 172
Speed Grade β€” -10 (10 ns tPD)
Pin-to-Pin Propagation Delay (tPD1, max) β€” 10 ns
Maximum Operating Frequency (fCNT) β€” 125 MHz
Supply Voltage - Core (VCCINT) β€” 3.3 V
Supply Voltage - I/O (VCCIO) β€” 3.3 V or 2.5 V
Input Voltage Tolerance β€” 5.0 V tolerant
Programmable Technology β€” EEPROM (in-system programmable)

Datasheets & Resources

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