EPM3512AFC256-7N vs EPM3512AFC256C Comparison
Detailed side-by-side comparison of EPM3512AFC256-7N by Altera and EPM3512AFC256C by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N ObsoleteIntel
EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256C β Last Time BuySpecification Comparison
| Parameter | EPM3512AFC256-7N | EPM3512AFC256C |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $61.00 | $27.95 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | β |
| User I/Os | 208 | β |
| Logic Blocks | 16 (32 macrocells each) | β |
| Propagation Delay (tPD) | 7.5 ns | β |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | β |
| 5V Tolerant I/O | Yes | β |
| In-System Programmability | IEEE Std. 1532 compliant | β |
| Programming Interface | JTAG (IEEE 1149.1) | β |
| Process Technology | CMOS EEPROM, 0.30 um | β |
| Package | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch | 256-ball FineLine BGA (FC) |
| Operating Temperature | 0 C to 70 C (commercial) | 0C to +70C (Commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum User I/Os | β | 208 |
| Dedicated Input Pins | β | 12 |
| Speed Grade | β | C (per datasheet ordering code) |
| Configuration Technology | β | EEPROM (non-volatile, instant-on) |
| Core Voltage | β | 3.3 V |
| I/O Standards Supported | β | MultiVolt: 5.0 V, 3.3 V, 2.5 V |
| JTAG Support | β | IEEE 1149.1 Boundary Scan |
| PCI Compliance | β | PCI SIG Local Bus Specification Revision 2.2 |
| Programming | β | In-system programmable via JTAG |