EPM3512AQ208-10N vs EPM3256AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQ208-10N by Altera and EPM3256AQC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQ208-10N EPM3256AQC208-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $21.40 $4.62
Family MAX 3000A β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 β€”
Usable Gates 10,000 10,000
User I/Os 172 β€”
Logic Array Blocks (LABs) 32 β€”
Package 208-pin PQFP β€”
Speed Grade -10 (10 ns pin-to-pin delay) β€”
Pin-to-Pin Delay (tPD) 4.5 ns (typical) β€”
Maximum Frequency (fCNT) 227.3 MHz β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 2.5 V, 3.3 V, or 5.0 V β€”
Process Technology CMOS EEPROM β€”
Programming Interface IEEE Std. 1532 (JTAG) ISP β€”
Operating Temperature (Industrial) -40 C to +85 C β€”
Mounting Type Surface Mount Surface Mount
RoHS Status unknown [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]
Series β€” MAX 3000A
Programmable Type β€” In-System Programmable (EEPROM)
Number of Macrocells β€” 256
Number of Logic Elements/Blocks β€” 16 LABs
Number of I/O Pins β€” 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) β€” 10 ns (max)
Maximum Counter Frequency β€” 227.3 MHz
Supply Voltage - Internal β€” 3.0 V to 3.6 V (3.3 V typical)
Operating Temperature β€” 0C to +70C (Commercial)
Package / Case β€” 208-BFQFP / 208-PQFP (28x28 mm)
ISP Compliance β€” IEEE Std. 1532
Boundary Scan β€” IEEE Std. 1149.1 (JTAG)
I/O Tolerance β€” 5 V tolerant, MultiVolt interface

Datasheets & Resources

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