EPM3512AQ208-10N vs EPM3512AQI208-10N Comparison
Detailed side-by-side comparison of EPM3512AQ208-10N by Altera and EPM3512AQI208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQ208-10N - MAX 3000A CPLD, 512 Macrocells, 172 I/O | Altera
EPM3512AQ208-10N ✓ ActiveSpecification Comparison
| Parameter | EPM3512AQ208-10N | EPM3512AQI208-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | — |
| Usable Gates | 10,000 | — |
| User I/Os | 172 | 172 (max), 208-pin package |
| Logic Array Blocks (LABs) | 32 | 12 |
| Package | 208-pin PQFP | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 4.5 ns (typical) | — |
| Maximum Frequency (fCNT) | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V, 3.3 V, or 5.0 V | — |
| Process Technology | CMOS EEPROM | — |
| Programming Interface | IEEE Std. 1532 (JTAG) ISP | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Operating Temperature (Industrial) | -40 C to +85 C | — |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | unknown | — |
| Logic Family | — | CMOS EEPROM-based |
| Macro Cells | — | 512 |
| Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage | — | 3.3 V |
| I/O Standards | — | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) |
| Package Type | — | PQFP-208 (FINE LINE BGA-style 256-pin land) |
| Pins | — | 256 (package), 208 used |
| Operating Temperature | — | 0C to 70C |
| Compliance | — | RoHS status unknown from data |
| Boundary Scan | — | Built-in BST (IEEE 1149.1) |
| Configuration Memory | — | On-chip EEPROM, non-volatile |