EPM3512AQC20-10 vs EPM3512AQ208-10N Comparison
Detailed side-by-side comparison of EPM3512AQC20-10 by Altera and EPM3512AQ208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQ208-10N - MAX 3000A CPLD, 512 Macrocells, 172 I/O | Altera
EPM3512AQ208-10N ✓ ActiveSpecification Comparison
| Parameter | EPM3512AQC20-10 | EPM3512AQ208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Active |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 32 |
| Macrocells per LAB | 32 | — |
| User I/O Pins | 100 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 4.5 ns (typical) |
| Maximum Frequency (fCNT) | 116.3 MHz | 227.3 MHz |
| Supply Voltage VCCINT | 5.0 V | — |
| MultiVolt I/O Voltages | 5.0 V / 3.3 V / 2.5 V / 1.8 V | — |
| Programming Interface | IEEE 1149.1 (JTAG) - In-System Programmable | IEEE Std. 1532 (JTAG) ISP |
| Process Technology | 0.30 µm EEPROM CMOS | CMOS EEPROM |
| Package | PQFP-240 (QC20 designation per Altera ordering code) | 208-pin PQFP |
| Operating Temperature | 0C to +70C (commercial) | — |
| RoHS Status | Compliant (lead-free PQFP package) | unknown |
| Usable Gates | — | 10,000 |
| User I/Os | — | 172 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V, 3.3 V, or 5.0 V |
| Operating Temperature (Industrial) | — | -40 C to +85 C |
| Mounting Type | — | Surface Mount |