EPM3512AQC208-10NS vs EPM3512AQC208-10 Comparison
Detailed side-by-side comparison of EPM3512AQC208-10NS by Altera and EPM3512AQC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3512AQC208-10NS | EPM3512AQC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 512 | — |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 12 | 32 |
| User I/Os | 172 | 208 |
| Pin-to-Pin Delay (tPD) | 10 ns (speed grade -10) | — |
| Internal Counter Frequency | 227.3 MHz max | — |
| Propagation Delay | 7.5 ns (datasheet figure) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Logic Family | CMOS, EEPROM-based | — |
| Configuration | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) | — |
| Package | 208-pin PQFP | 208-pin PQFP |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70 C (commercial) |
| ISP Standard | IEEE Std. 1532 | — |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status not in verified data] |
| Mounting Type | Surface Mount | — |
| Macrocells | — | 512 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE Std. 1532) |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |
| PCI Compliance | — | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) |