EPM3512AQC208-15N vs EPM3512AQC208-10 Comparison
Detailed side-by-side comparison of EPM3512AQC208-15N by Altera and EPM3512AQC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera
EPM3512AQC208-15N ⚠ Last Time BuySpecification Comparison
| Parameter | EPM3512AQC208-15N | EPM3512AQC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 32 |
| Maximum User I/O Pins | 172 | — |
| Typical Usable Gates | 12,000 | — |
| Number of Logic Elements | 512 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Operating Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt) | — |
| Programmable I/O Standards | LVTTL, LVCMOS, PCI (with external resistor) | — |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | Yes (IEEE Std. 1532) |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| JTAG Support | Yes (BST/Boundary-Scan Test) | — |
| Package | PQFP-208 (QC208) | 208-pin PQFP |
| Mounting Type | Surface Mount | — |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70 C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in verified data] |
| Usable Gates | — | 10,000 |
| Macrocells | — | 512 |
| User I/Os | — | 208 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |
| PCI Compliance | — | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) |