EPM3512AQC208-3N vs EPM3512AQC208-7 Comparison
Detailed side-by-side comparison of EPM3512AQC208-3N by Altera and EPM3512AQC208-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 NrndSpecification Comparison
| Parameter | EPM3512AQC208-3N | EPM3512AQC208-7 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| User I/O Pins | 172 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Macrocells per LAB | 32 | — |
| Pin-to-Pin Logic Delay | 3 ns (speed grade -3) | — |
| Global Clock Setup Time | [DATA_NEEDED: actual tSU at 3 ns grade] | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) | — |
| Operating Temperature | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Package | PQFP-208 | 208-Pin PQFP (FQFP, gull-wing) |
| Mounting Type | Surface Mount | — |
| Programming Technology | EEPROM (non-volatile, in-system programmable) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| ISP Compliance | IEEE Std. 1532 | — |
| RoHS Status | [DATA_NEEDED: not stated in retrieved snippets] | Compliant |
| Lead-Free / Halogen-Free | [DATA_NEEDED] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 10,000 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Counter Frequency (fCNT) | — | 116.3 MHz |
| User I/Os | — | 172 |
| Logic Elements / LEs | — | N/A (CPLD macrocell architecture) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standards Supported | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Programming | — | In-System Programmable via JTAG (IEEE Std. 1532) |
| Process Technology | — | CMOS EEPROM, 0.30 um |
| Lead-Free | — | Yes |