EPM3512AQC208-3N vs EPM3512AQC208-7 Comparison

Detailed side-by-side comparison of EPM3512AQC208-3N by Altera and EPM3512AQC208-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-3N EPM3512AQC208-7
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $16.40 $41.72
Family MAX 3000A MAX 3000A
Macrocells 512 512
User I/O Pins 172 β€”
Logic Array Blocks (LABs) 16 β€”
Macrocells per LAB 32 β€”
Pin-to-Pin Logic Delay 3 ns (speed grade -3) β€”
Global Clock Setup Time [DATA_NEEDED: actual tSU at 3 ns grade] β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) β€”
Operating Temperature 0C to +70C (commercial) 0 C to +70 C (commercial)
Package PQFP-208 208-Pin PQFP (FQFP, gull-wing)
Mounting Type Surface Mount β€”
Programming Technology EEPROM (non-volatile, in-system programmable) β€”
JTAG / Boundary Scan IEEE 1149.1 compliant β€”
ISP Compliance IEEE Std. 1532 β€”
RoHS Status [DATA_NEEDED: not stated in retrieved snippets] Compliant
Lead-Free / Halogen-Free [DATA_NEEDED] β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Usable Gates β€” 10,000
Propagation Delay (tPD) β€” 7.5 ns
Counter Frequency (fCNT) β€” 116.3 MHz
User I/Os β€” 172
Logic Elements / LEs β€” N/A (CPLD macrocell architecture)
Supply Voltage (VCCINT) β€” 3.3 V
I/O Standards Supported β€” 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O)
Programming β€” In-System Programmable via JTAG (IEEE Std. 1532)
Process Technology β€” CMOS EEPROM, 0.30 um
Lead-Free β€” Yes

Datasheets & Resources

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