EPM3512AQC20810 vs EPM3512AQC208-7N Comparison

Detailed side-by-side comparison of EPM3512AQC20810 by Altera and EPM3512AQC208-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AQC20810 EPM3512AQC208-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Family MAX 3000A MAX 3000A
Logic Type CPLD (EEPROM-based, non-volatile) —
Macro Cells 512 —
User I/Os 172 172
Logic Array Blocks (LABs) 16 32
Usable Gates (equivalent) 10000 —
Package 208-pin PQFP (PQ208) 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing)
Speed Grade -10 (tPD = 10 ns) -7
Propagation Delay (tPD) 10 ns 7.5 ns
Maximum Internal Frequency 132 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V —
In-System Programmability Yes (IEEE 1149.1 JTAG, 3.3 V ISP) —
PCI Compliance PCI Local Bus Specification Revision 2.2 compliant —
Operating Temperature (commercial) 0 °C to +70 °C —
Process Technology 0.30 µm CMOS EEPROM 0.30 µm CMOS EEPROM
Configuration Memory On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention —
RoHS Status [DATA_NEEDED: RoHS status] Compliant
Logic Capacity — 512 macrocells, 10,000 usable gates
Macrocells per LAB — 16
Maximum Frequency (fCNT) — 116.3 MHz
Supply Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Bank Count — 4 (MultiVolt)
Supported I/O Standards — 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS
Configuration — Non-volatile EEPROM, in-system programmable (ISP)
JTAG Interface — IEEE 1149.1 BST + IEEE 1532 ISP
Operating Temperature — 0 °C to +70 °C (commercial)

Datasheets & Resources

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