EPM5032LC-15 vs EPM5032LC-25 Comparison
Detailed side-by-side comparison of EPM5032LC-15 by Altera and EPM5032LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032LC-15 | EPM5032LC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 5000 EPLD | — |
| Architecture | PAL-type AND/OR with PIA | PAL-type EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 600 | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 4 | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Maximum Operating Frequency | 83.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V ±10% (4.5 V to 5.5 V) |
| Technology | CMOS EPROM, 1.0 um process | CMOS, UV-erasable / OTP |
| Programmability | UV-Erasable / OTP | — |
| Package | JLCC-28 (windowed ceramic) | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch |
| Operating Temperature | 0C to +70C (commercial) | 0 °C to +70 °C (commercial, "LC" suffix) |
| RoHS Status | Non-compliant (contains Pb, ceramic-windowed package) | Not RoHS compliant (legacy Altera product) |
| Device Family | — | MAX 5000 |
| Product Terms | — | 320 |
| I/O Pins | — | 16 bidirectional |
| Total Inputs | — | 24 (7 dedicated + 16 I/O used as input) |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Internal Frequency | — | 62.5 MHz |
| I/O Standard | — | 5 V CMOS |
| Mounting Type | — | Surface Mount, socket-compatible |
| Configuration Cell | — | Programmable interconnect array (PIA), OTP / UV-erasable |