EPM5032LC-20 vs EPM5016LC-17 Comparison
Detailed side-by-side comparison of EPM5032LC-20 by Altera and EPM5016LC-17 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032LC-20 | EPM5016LC-17 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | EPLD / CPLD (One-Time Programmable / UV-Erasable) | — |
| Usable Gates | 600 gates | — |
| Macrocells | 32 | 16 |
| Logic Blocks (LABs) | 1 | — |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Maximum Frequency | 71.4 MHz | — |
| Propagation Delay (tPD) | 20 ns | 17 ns |
| Supply Voltage (VCC) | 5 V ±5% | — |
| Operating Temperature | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) | [DATA_NEEDED: temperature grade] |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs | 24 | — |
| Output Functions | 16 | — |
| Product Terms per Output | 16 | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Package | LCC-28 (Plastic Leaded Chip Carrier, J-lead) | Windowed Ceramic DIP (LC) |
| Mounting Type | Surface Mount | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| MSL Level | [DATA_NEEDED: MSL] | — |
| Family | — | MAX 5000 EPLD |
| Technology | — | CMOS, UV-erasable |
| Product Terms | — | 160 |
| I/O Pins | — | 8 |
| Total Input Pins | — | 16 |
| Outputs | — | 8 |
| External Clock Inputs | — | 1 |
| Architecture | — | PAL-type with Programmable Interconnect Array (PIA) |
| Supply Voltage | — | [DATA_NEEDED: VCC range] |
| Logic Compatibility | — | TTL/CMOS |