EPM5064JC-1 vs EPM5064LC-1 Comparison

Detailed side-by-side comparison of EPM5064JC-1 by Altera and EPM5064LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064JC-1 EPM5064LC-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) —
Macro Cells 64 —
Usable Gates 1250 (typical) 1.25K (approx.)
Logic Elements 128 (Logic Array Blocks) —
Maximum Operating Frequency 33.3 MHz (fCNT) —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD typical/max in ns] —
Supply Voltage (VCC) 5 V nominal (4.75 V – 5.25 V) 4.75 V to 5.25 V
Process Technology 0.8 µm CMOS CMOS
Programmable Pins 36 (typical I/O, 44-pin PLCC) —
Dedicated Inputs [DATA_NEEDED: dedicated input count] 7
Package 44-pin PLCC (J-lead, windowed ceramic) 44-pin PLCC (Plastic Leaded Chip Carrier)
Mounting Type Surface Mount (PLCC socket recommended) —
Operating Temperature 0 °C to +70 °C (commercial, -JC suffix) [DATA_NEEDED: operating temperature range]
Erasure Method UV-erasable through quartz window —
Programming Method Altera Logic Programmer + MasterBlaster/ByteBlasterMV —
JTAG Boundary Scan Not supported (classic MAX architecture) —
RoHS Status Non-compliant (windowed ceramic, contains Pb in glass frit) [DATA_NEEDED: RoHS compliance]
Military/Avionics SMD 5962-01-417-3750 (QML variant: EPM5064JM/883) —
Product Type — CPLD (Complex Programmable Logic Device)
Macrocells — 64
Logic Array Blocks (LABs) — 4
Internal Operating Frequency — 62.5 MHz
Propagation Delay (tPD) — 40 ns
Input Lines — 36
Output Lines — 28
Programming Technology — OTP / UV-Erasable EPROM
Programming Interface — JTAG (ByteBlaster-compatible)

Datasheets & Resources

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