EPM5128GC-2 vs EPM5064LC Comparison
Detailed side-by-side comparison of EPM5128GC-2 by Altera and EPM5064LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128GC-2 | EPM5064LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Logic Elements / Gates | 2,500 usable gates | — |
| Macrocells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Maximum Operating Frequency | 50 MHz | — |
| Propagation Delay (tPD) | Approx. 25 ns (typical, -2 speed grade) | 55 ns |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V |
| Package Type | 68-pin PGA (Pin Grid Array) | — |
| Package Code (per Partstack) | WPGA | — |
| Number of Terminals | 68 | — |
| Programming Technology | UV-erasable EPROM | — |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Grade (per Partstack) | COMMERCIAL | — |
| Terminal Form | PIN/PEG | — |
| Configuration Memory | Non-volatile, one-time programmable (erasable via UV) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programming Type | — | OTP (One-Time-Programmable, UV-erasable EPROM) |
| Macro Cells | — | 64 |
| Usable Gates | — | 1.25K |
| Logic Array Blocks (LABs) | — | 4 |
| Total Inputs | — | 36 (7 dedicated + 29 I/O) |
| I/O Pins | — | 28 bidirectional + 4 dedicated input |
| Package | — | PLCC-44 (LCC-44, J-lead) |
| Process Technology | — | CMOS EPROM |
| Mounting Type | — | Surface Mount |
| RoHS Status | — | [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] |
| Lead Free | — | [DATA_NEEDED: lead-free status] |