EPM5130GI vs EPM5128LC-1 Comparison
Detailed side-by-side comparison of EPM5130GI by Altera and EPM5128LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130GI | EPM5128LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Architecture | EPLD (Erasable Programmable Logic Device), UV-erasable | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Dedicated Inputs | 19 | 7 |
| Total Inputs | 68 | — |
| I/O Pins | 48 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | — |
| External Clock Pins | 1 | — |
| Process Technology | CMOS | CMOS EPROM, UV-erasable |
| Supply Voltage | 5 V | — |
| Package | Ceramic Pin Grid Array (PGA), windowed | — |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Programming Method | UV erasure + EPROM programming | — |
| Family | — | MAX 5000 |
| Logic Elements / Macrocells | — | 128 macrocells |
| Number of Usable Gates | — | [DATA_NEEDED: usable gates] |
| Bidirectional I/O Pins | — | 52 |
| Total User I/O | — | 60 (max) |
| Propagation Delay (tpd) | — | 30 ns |
| Supply Voltage (VCC) | — | 5 V (±10%) |
| Programmability | — | UV-erasable / OTP (windowed package) |
| Package Type | — | 68-pin J-lead ceramic chip carrier (PLCC windowed) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Mounting Type | — | Surface Mount (J-lead PLCC socket compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |