EPM5130JI vs EPM5130WC-1 Comparison
Detailed side-by-side comparison of EPM5130JI by Altera and EPM5130WC-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000
EPM5130WC-1 ObsoleteSpecification Comparison
| Parameter | EPM5130JI | EPM5130WC-1 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-Erasable EPLD (CMOS EPROM) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum Clock Frequency | 33.3 MHz | 50 MHz |
| Propagation Delay (tPD) | 55 ns | — |
| External Clock Inputs | 1 (shared input/clock) | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Process Technology | 0.75 micron CMOS EPROM | CMOS EPROM |
| Supply Voltage | 5 V (typical) | [DATA_NEEDED: VCC nominal] |
| Input Logic Standard | TTL-compatible | — |
| Package Type | Ceramic J-Leaded Chip Carrier (JLCC) with UV window | 100-pin Ceramic QFP (Windowed) |
| Operating Temperature | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| Program/Erase Method | UV erasure through quartz window | — |
| RoHS Status | Non-compliant (contains Pb in ceramic package) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Obsolete - EOL by Altera/Intel | — |
| Series | — | MAX 5000 |
| Manufacturer | — | Altera (now Intel) |
| Macrocell Count | — | 128 |
| Logic Array Blocks | — | Multiple LABs (per MAX 5000 architecture) |
| Propagation Delay (tpd) | — | 40 ns |
| Erasure Method | — | UV (ultraviolet, windowed package) |
| User I/O Pins | — | Up to 100 |
| Programmable | — | Yes (UV-erasable, non-volatile) |
| Logic Family | — | MAX 5000 (Altera) |
| Configuration Memory | — | EPROM (on-chip) |
| Mounting Type | — | Surface Mount |