EPM5192AJC-15 vs EPM5192AJC84-20 Comparison
Detailed side-by-side comparison of EPM5192AJC-15 by Intel and EPM5192AJC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AJC-15 | EPM5192AJC84-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-erasable/OTP Complex PLD (CPLD) |
| Macrocells | 192 | 192 |
| Logic Capacity | 100% connectivity, sum-of-products PLA architecture | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Operating Temperature | 0C to +70C (commercial) | — |
| Package | 84-pin PLCC (J-lead, ceramic, non-windowed) | 84-pin PLCC J-Lead (WQCCJ, J84) |
| Mounting Type | Surface Mount | Surface Mount (J-Lead) |
| Programmability | UV-erasable (windowed variant) / One-Time-Programmable | — |
| Toolchain | MAX+PLUS II | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Pin Count | 84 | — |
| User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Speed Grades Available | -15, -20, -25 (this part: -15) | — |
| Configuration Memory | EPROM (UV-erasable) | — |
| Propagation Delay (tpd) | — | 33 ns (speed grade -20) |
| Maximum Clock Frequency | — | 66.7 MHz |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V |
| Dedicated Inputs | — | 7 |
| User I/O Lines | — | 64 |
| Process Technology | — | CMOS, UV-erasable EEPROM |
| Operating Temperature Grade | — | Commercial |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus (legacy) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |