EPM5192AJC-25 vs EPM5192AJC84-20 Comparison
Detailed side-by-side comparison of EPM5192AJC-25 by Altera and EPM5192AJC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AJC-25 | EPM5192AJC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 |
| Manufacturer | Altera (now Intel PSG) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 25 ns | — |
| Package | PLCC-68 (windowed ceramic, AJC) | 84-pin PLCC J-Lead (WQCCJ, J84) |
| Pin Count | 68 | — |
| Mounting Type | Surface Mount | Surface Mount (J-Lead) |
| Supply Voltage | 5 V (typical) | — |
| Logic Blocks | MAX 5000 LABs (Logic Array Blocks) | — |
| Programmable Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Operating Temperature | [DATA_NEEDED: exact operating temperature range] | — |
| Erasure Method | UV-erasable (windowed ceramic package) | — |
| Programming Technology | EPROM (non-volatile) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Military Grade | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) | — |
| Device Type | — | UV-erasable/OTP Complex PLD (CPLD) |
| Propagation Delay (tpd) | — | 33 ns (speed grade -20) |
| Maximum Clock Frequency | — | 66.7 MHz |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V |
| Dedicated Inputs | — | 7 |
| User I/O Lines | — | 64 |
| Process Technology | — | CMOS, UV-erasable EEPROM |
| Operating Temperature Grade | — | Commercial |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus (legacy) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |