EPM5192AQC-2 vs EPM5192AGC-20 Comparison
Detailed side-by-side comparison of EPM5192AQC-2 by Altera and EPM5192AGC-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192AQC-2 | EPM5192AGC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | EPLD (EEPLD, UV-erasable) |
| Series | MAX 5000 (EPM5192) | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 20 ns |
| Maximum Clock Frequency | [DATA_NEEDED: max fMAX for -2 grade] | — |
| Process Technology | CMOS | — |
| Switch Matrix | UV-Erasable / OTP (windowless on AQC package) | — |
| Package | 100-pin PQFP (R-PQFP-G100) | PGA-132 (ceramic windowed, 'GC') |
| Lead Pitch | 0.635 mm | — |
| Terminal Form | Gull-wing | — |
| Operating Temperature | [DATA_NEEDED: commercial / industrial / military grade] | 0C to 70C (commercial) |
| Mounting Type | Surface Mount | Through-hole (PGA socket) |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | IEEE 1149.1 JTAG |
| RoHS Status | [DATA_NEEDED: confirmed compliance status] | [DATA_NEEDED: RoHS status - ceramic PGA windowed parts are typically pre-RoHS] |
| Family | — | MAX 5000 |
| Usable Gates | — | 12,000 |
| Counter Frequency (fCNT) | — | 100 MHz (max) |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Logic Array Blocks (LABs) | — | 8 |
| Dedicated I/O Pins | — | 96 |
| In-System Programmability | — | Yes (5 V ISP) |
| Security Bit | — | Yes (pattern read-back protected) |