EPM5192AQC-2 vs EPM5192AQI100-20 Comparison
Detailed side-by-side comparison of EPM5192AQC-2 by Altera and EPM5192AQI100-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AQI100-20 - MAX 5000 192-Macrocell EPLD, 20ns, PQFP-100 | Altera
EPM5192AQI100-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AQC-2 | EPM5192AQI100-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | — |
| Series | MAX 5000 (EPM5192) | — |
| Macrocells | 192 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | — |
| Maximum Clock Frequency | [DATA_NEEDED: max fMAX for -2 grade] | — |
| Process Technology | CMOS | — |
| Switch Matrix | UV-Erasable / OTP (windowless on AQC package) | — |
| Package | 100-pin PQFP (R-PQFP-G100) | 100-pin PQFP (R-PQFP-G100) |
| Lead Pitch | 0.635 mm | — |
| Terminal Form | Gull-wing | — |
| Operating Temperature | [DATA_NEEDED: commercial / industrial / military grade] | Industrial grade ("I" suffix) |
| Mounting Type | Surface Mount | Surface Mount (PQFP) |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | — |
| RoHS Status | [DATA_NEEDED: confirmed compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 5000 EPLD |
| Device Series | — | EPM5192 |
| Technology | — | CMOS, UV-erasable EPROM |
| Propagation Delay | — | 20 ns (speed grade -20) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Macrocell Count | — | 192 |
| I/O Pins | — | 64 bidirectional |
| JEDEC Package Outline | — | R-PQFP-G100 |
| Architecture | — | Classic EPLD, deterministic timing |
| Design Tool | — | Altera MAX+PLUS II (legacy) |
| Supply Voltage | — | [DATA_NEEDED: VCC range] |