EPM5192AQC100-15 vs EPM5192AQM100-15 Comparison
Detailed side-by-side comparison of EPM5192AQC100-15 by Altera and EPM5192AQM100-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192AQC100-15 | EPM5192AQM100-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel) | — |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | EPLD (Erasable PLD) |
| Technology | CMOS | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | 12 |
| Propagation Delay (tPD) | 25 ns (-15 speed grade) | — |
| Total Inputs | 72 | 72 |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| External Clock Inputs | 1 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Package | 100-pin PQFP (R-PQFP-G100) | PQFP-100 (R-PQFP-G100) |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EPROM (UV-erasable, OTP) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Interconnect Architecture | — | Product Term Sharing (PIA) |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Speed Grade | — | -15 (15 ns macrocell delay) |
| Process Technology | — | CMOS |
| Programming Technology | — | EPROM (UV-erasable) |
| Supply Voltage | — | 5 V (typical, single supply) |