EPM5192JC vs EPM5192JC-1N Comparison
Detailed side-by-side comparison of EPM5192JC by Intel and EPM5192JC-1N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC | EPM5192JC-1N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Package | 68-pin PLCC (JC) windowed ceramic | 84-pin Ceramic Quad Flat Pack (CQFP) |
| Mounting Type | Surface Mount | — |
| Programming Method | UV-erase + EPROM programmer | — |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| Operating Temperature | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: industrial/commercial temperature range] |
| Supply Voltage | [DATA_NEEDED: VCC nominal] | — |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| RoHS Status | [DATA_NEEDED: original Altera marking not RoHS] | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Usable Gates | — | 3750 |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs (GCLK) | — | 1 |
| Propagation Delay (tPD) | — | 40 ns |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS EPROM (UV-erasable) |
| JEDEC Package Code | — | S-CQCC-J84 |
| Programming Interface | — | JTAG / Altera ByteBlaster |