EPM5192LC-45 vs EPM5192LC Comparison
Detailed side-by-side comparison of EPM5192LC-45 by Altera and EPM5192LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-45 | EPM5192LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $24.00 | $28.40 |
| Family | MAX 5000 | MAX 7000S |
| Series | EPM5192 | β |
| Macrocells | 192 | 192 |
| Logic Elements | 192 macrocells | β |
| Maximum Operating Frequency | 100 MHz | β |
| Pin-to-Pin Delay (tPD) | 45 ns | β |
| Dedicated Inputs | [DATA_NEEDED: dedicated input count] | 7 |
| Programmable I/O Pins | [DATA_NEEDED: I/O pin count] | β |
| Configuration Memory | UV-erasable EPROM / OTP | β |
| Technology | EPROM-based CMOS | β |
| Package Type | LCC (Leaded Ceramic Chip Carrier) with UV window | β |
| Package Code | LC | β |
| Speed Grade | -45 (45 ns tPD) | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| Supply Voltage | 5 V | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Mounting Type | Surface Mount (LCC) | Surface Mount |
| Datasheet Page Count | 52 pages | β |
| Logic Array Blocks (LABs) | β | 12 |
| User I/O Pins | β | 64 |
| Global Clock Inputs | β | 1 |
| Propagation Delay (tPD) | β | 55 ns (typical, commercial) |
| Maximum Clock Frequency (fMAX) | β | 50 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | β | CMOS, UV-erasable/OTP EPROM configuration |
| Programmable Interconnect | β | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | β | JTAG IEEE 1149.1 |
| Programming Interface | β | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | β | 0C to +70C |
| Package | β | JLCC-68 (windowed ceramic, LC suffix) |