EPM7128SQC100-10 vs EPM7128SQI100-10 Comparison
Detailed side-by-side comparison of EPM7128SQC100-10 by Altera and EPM7128SQI100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
EPM7128SQI100-10 ObsoleteSpecification Comparison
| Parameter | EPM7128SQC100-10 | EPM7128SQI100-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | 128 |
| Logic Elements / Gates | 2,500 usable gates | — |
| Maximum User I/O | 84 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 100 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Supply Voltage | 5 V | — |
| Process Technology | 5V CMOS, EEPROM-based | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) | — |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (Industrial) |
| Mounting Type | Surface Mount | — |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status not in provided data] |
| User I/Os | — | 84 |
| Usable Gates | — | 2,500 |
| Logic Blocks (LABs) | — | 8 (16 macrocells each) |
| Package Type | — | PQFP-100 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 125 MHz to 250 MHz |
| Counter Speed | — | Up to 175.4 MHz |
| Operating Voltage (VCC) | — | 5 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| Program/Erase Cycles | — | 100 minimum |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Logic Family | — | CMOS |
| I/O Compatibility | — | TTL-compatible, 5V/3.3V multi-voltage |