EPM7128STC100-10 vs EPM7128SQC100-10 Comparison
Detailed side-by-side comparison of EPM7128STC100-10 by Altera and EPM7128SQC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 Obsolete
Specification Comparison
| Parameter | EPM7128STC100-10 | EPM7128SQC100-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | — |
| Logic Array Blocks | 8 (16 macrocells per LAB) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family | CMOS | — |
| Supply Voltage (VCCINT) | 5 V | — |
| MultiVolt I/O Voltage | 3.3 V / 5 V | — |
| Package | TQFP-100 (C100) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Pin Count | 100 | — |
| Mounting Type | Surface Mount | Surface Mount |
| Programmability | In-System Programmable (JTAG, IEEE 1149.1), EEPROM | In-System Programmable (ISP) via JTAG |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status not in provided data] | [DATA_NEEDED: rohs_status] |
| Logic Elements / Gates | — | 2,500 usable gates |
| Maximum User I/O | — | 84 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Operating Frequency | — | 100 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Supply Voltage | — | 5 V |
| Process Technology | — | 5V CMOS, EEPROM-based |