EPM7160SQC160-10 vs EPM7192SQC160-10N Comparison
Detailed side-by-side comparison of EPM7160SQC160-10 by Altera and EPM7192SQC160-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 ObsoleteAltera
EPM7192SQC160-10N - 192-Macrocell MAX 7000S CPLD, 10ns, 160-Pin PQFP | Altera
EPM7192SQC160-10N NrndSpecification Comparison
| Parameter | EPM7160SQC160-10 | EPM7192SQC160-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 7000S | MAX 7000 |
| Macro Cells | 160 | — |
| Logic Elements / Gates | 3,200 usable gates | — |
| User I/Os | 104 | — |
| Logic Array Blocks (LABs) | 10 | 12 |
| Maximum Operating Frequency | 100 MHz | 100 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| I/O Voltage Tolerance | 5.0 V | — |
| Programming Technology | EEPROM, in-system programmable | — |
| JTAG Support | IEEE 1149.1 (boundary-scan + ISP) | — |
| Package | PQFP-160 (SQC160) | — |
| Operating Temperature | 0 C to +70 C (commercial) | [DATA_NEEDED: commercial/industrial grade] |
| Logic Family | CMOS | — |
| Mounting Type | Surface Mount | Surface Mount |
| Process Technology | CMOS, EEPROM-based | 0.30 µm CMOS EEPROM |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | unknown | — |
| Series | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 192 |
| Usable Gates | — | 3,750 |
| User I/O Pins | — | 124 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Package / Case | — | 160-BQFP (PQFP, 0.65 mm pitch) |