EPM7192SQC160-10N vs EPM7160SQC160-10 Comparison
Detailed side-by-side comparison of EPM7192SQC160-10N by Altera and EPM7160SQC160-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192SQC160-10N - 192-Macrocell MAX 7000S CPLD, 10ns, 160-Pin PQFP | Altera
EPM7192SQC160-10N NrndAltera
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 ObsoleteSpecification Comparison
| Parameter | EPM7192SQC160-10N | EPM7160SQC160-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Series | MAX 7000S | — |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | 10 |
| Usable Gates | 3,750 | — |
| User I/O Pins | 124 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | 100 MHz |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| Process Technology | 0.30 µm CMOS EEPROM | CMOS, EEPROM-based |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Package / Case | 160-BQFP (PQFP, 0.65 mm pitch) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: commercial/industrial grade] | 0 C to +70 C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| Macro Cells | — | 160 |
| Logic Elements / Gates | — | 3,200 usable gates |
| User I/Os | — | 104 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| I/O Voltage Tolerance | — | 5.0 V |
| Programming Technology | — | EEPROM, in-system programmable |
| JTAG Support | — | IEEE 1149.1 (boundary-scan + ISP) |
| Package | — | PQFP-160 (SQC160) |
| Logic Family | — | CMOS |
| Lead-Free | — | unknown |