EPM7192SQC160-10N vs EPM7192SQC160-15 Comparison
Detailed side-by-side comparison of EPM7192SQC160-10N by Altera and EPM7192SQC160-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192SQC160-10N - 192-Macrocell MAX 7000S CPLD, 10ns, 160-Pin PQFP | Altera
EPM7192SQC160-10N Nrnd
Specification Comparison
| Parameter | EPM7192SQC160-10N | EPM7192SQC160-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Series | MAX 7000S | — |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Usable Gates | 3,750 | — |
| User I/O Pins | 124 | 124 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | 76.9 MHz |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Process Technology | 0.30 µm CMOS EEPROM | CMOS, EEPROM-based |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Package / Case | 160-BQFP (PQFP, 0.65 mm pitch) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: commercial/industrial grade] | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | — |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of Usable Gates | — | 3750 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns |
| Supply Voltage | — | 5.0 V |
| Programmability | — | In-System (ISP) via JTAG IEEE Std 1149.1 |
| Configuration Memory | — | EEPROM, non-volatile |
| Package | — | PQFP-160 |
| Operating Temperature Range | — | [DATA_NEEDED: operating temperature range] |