EPM7192SQC160-15 vs EPM7160SQC160-10 Comparison
Detailed side-by-side comparison of EPM7192SQC160-15 by Altera and EPM7160SQC160-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 ObsoleteSpecification Comparison
| Parameter | EPM7192SQC160-15 | EPM7160SQC160-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Number of Macrocells | 192 | — |
| Number of Logic Array Blocks | 4 | — |
| Number of Usable Gates | 3750 | — |
| User I/O Pins | 124 | — |
| Pin-to-Pin Logic Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 76.9 MHz | 100 MHz |
| Supply Voltage | 5.0 V | — |
| Programmability | In-System (ISP) via JTAG IEEE Std 1149.1 | — |
| Configuration Memory | EEPROM, non-volatile | — |
| Package | PQFP-160 | PQFP-160 (SQC160) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | — |
| Process Technology | CMOS, EEPROM-based | CMOS, EEPROM-based |
| Macro Cells | — | 160 |
| Logic Elements / Gates | — | 3,200 usable gates |
| User I/Os | — | 104 |
| Logic Array Blocks (LABs) | — | 10 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Voltage Tolerance | — | 5.0 V |
| Programming Technology | — | EEPROM, in-system programmable |
| JTAG Support | — | IEEE 1149.1 (boundary-scan + ISP) |
| Operating Temperature | — | 0 C to +70 C (commercial) |
| Logic Family | — | CMOS |
| RoHS Status | — | unknown |
| Lead-Free | — | unknown |