EPM7192SQC160-15 vs EPM7192SQC160-7N Comparison
Detailed side-by-side comparison of EPM7192SQC160-15 by Altera and EPM7192SQC160-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192SQC160-7N - MAX 7000S 192-Macro CPLD, 7.5ns, PQFP-160 | Altera
EPM7192SQC160-7N ObsoleteSpecification Comparison
| Parameter | EPM7192SQC160-15 | EPM7192SQC160-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Number of Macrocells | 192 | — |
| Number of Logic Array Blocks | 4 | — |
| Number of Usable Gates | 3750 | — |
| User I/O Pins | 124 | — |
| Pin-to-Pin Logic Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| Supply Voltage | 5.0 V | — |
| Programmability | In-System (ISP) via JTAG IEEE Std 1149.1 | EEPROM, In-System (JTAG ISP) |
| Configuration Memory | EEPROM, non-volatile | — |
| Package | PQFP-160 | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | — |
| Process Technology | CMOS, EEPROM-based | — |
| Logic Family | — | CMOS |
| Macro Cells | — | 192 |
| Usable Gates | — | 3,750 |
| User I/Os | — | 124 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Internal Counter Frequency | — | 167 MHz |
| Pin Count | — | 160 |
| Package Type | — | PQFP (Plastic Quad Flat Pack) |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Voltage (VCCIO) | — | 3.3 V / 5.0 V selectable |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| Operating Temperature | — | 0 C to 70 C (Commercial) |
| Lead-Free (Pb-Free) | — | Yes (N suffix) |
| RoHS Status | — | Compliant (Pb-free terminal finish) |