EPM7256AETC100-7 vs EPM7256AETC100-5N Comparison
Detailed side-by-side comparison of EPM7256AETC100-7 by Intel and EPM7256AETC100-5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7256AETC100-7 - 256-Macrocell MAX 7000A CPLD, 7.5ns TQFP-100 | Intel
EPM7256AETC100-7 ObsoleteSpecification Comparison
| Parameter | EPM7256AETC100-7 | EPM7256AETC100-5N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Family | MAX 7000A | MAX 7000A |
| Series | EPM7256 | MAX 7000AE |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Technology | EEPROM-based, CMOS | — |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | 5000 (range 600 to 10000) |
| Number of I/Os | 84 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Core Supply Voltage | 3.3 V | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 5.0 ns |
| Maximum Operating Frequency | 126.6 MHz | — |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Package | TQFP-100 (ET100) | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) - In-System Programmable | — |
| RoHS Status | Unknown - part marked obsolete | Compliant (lead-free) |
| Memory Type | EEPROM (non-volatile) | — |
| Macro Cells | — | 256 |
| User I/Os | — | 84 |
| Logic Array Blocks (LABs) | — | 16 |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| MultiVolt I/O Support | — | 2.5 V / 3.3 V / 5.0 V |
| Program Memory | — | Internal EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| MSL Level | — | 3 (168 hours) |
| Process Technology | — | CMOS, EEPROM-based |
| Security Bit | — | Programmable |